Digital electronic circuits that operate as edge-triggered flip-flops are a widely-used industry-standard building block. Common edge-triggered flip-flops have a single clock input which is sensitive to a single polarity of level transition, either low-to-high or high-to-low, with specific polarity for the device designed-in at the time of manufacture. The typical edge-triggered flip-flop design also has a small number (usually one or two) of synchronous control inputs which are sampled by the device on each occurrence of the predetermined sensitive edge of the clock input. The output or outputs of the edge-triggered flip-flop then are switched by the device to new values according to the sampled input or inputs. For example, the simplest variety of edge-triggered flip-flop is the common type-D flip-flop, which has a single synchronous control input, referred to as the D or data input, and an output, referred to as the Q output, which follows simply the data input logic level at each sensitive edge of the clock. A second output, referred to as the not-Q, Q-false, or Q-bar output, may be provided, which is the logical inverse of the Q output.
Using conventional circuitry, it is difficult to increase the rate of signal output for a given clock signal. This makes the design of circuits for certain outputs impractical, if not impossible. For example, using conventional counter technology, it is very difficult to produce counters that with an even duty cycle, divide by an odd number or that divide-by-(n/2), where n is an odd integer. As a result, there is a need to design a simple circuit that can address these limitations for digital electronic circuits.
It is an object of the present invention, therefore, to provide a simple, easy-to-implement circuit that makes simple the use of double-clock inputs or use of both the rising and falling edge of a single clock input. As such, the present invention solves the limitations in existing digital electronic circuit designs by providing a double-clock flip-flop circuit that produces a circuit output signal in response to two clock signals by using a first flip-flop for producing a first output signal in response to a first clock signal and a second flip-flop for producing a second output signal in response to a second clock signal, then a means for generating an input data signal to the first flip-flop in response to the second output signal combined with a means for producing the circuit output signal in response to exclusively either the first flip-flop producing the first output signal or the second flip-flop producing the second output signal. As a result, the circuit is responsive to two clock input signals.
It is also an object of the present invention to provide a synchronous logic circuit that is sensitive to both edges of a clock signal and that may be used as either a D or J-K flip-flop circuit.
Further, it is an object of the present invention to reduce system clock rates and increase the speed of a counter circuit by using both edges of a single clock input.
Moreover, it is an object of the present invention to provide a circuit that permits both edges of a clock signal to directly control the circuit output signal.
It is a yet another object of the present invention to provide a circuit that has many possible applications for uses requiring double-edge, single-data flip-flops as well as a double-edge, J-K flip-flop output that may be used in various applications such as in counter circuits, shift registers, and state machines.